Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. The schematic diagram or HDL specification is then synthesized into cells of a cell library, the cells are placed in a layout pattern and interconnections are routed along predetermined routing layers. Once the final design has been completed, the resulting netlist, cell layout definitions, placement data and routing data together form an integrated circuit layout definition, which can be used to fabricate the integrated circuit.
Logic resynthesis refers to steps that can be performed during the design process to optimize one or more design characteristic, such as timing. For example, resynthesis can be used to optimize logic trees, large trees of buffers and inverters, cell types and placement. Resynthesis can be performed on local and global levels.
Throughout the resynthesis process, the integrated circuit design is changed step by step, by applying procedures of local optimization.
Many of the resynthesizing steps, such as design restructuring, can be performed prior to routing. However due to the large number of interconnections, or “nets”, in a typical design, this restructuring can have a great effect on routing congestion in certain areas of the chip. This can complicate the routing process.
Limiting or controlling routing congestion during logic resynthesis would therefore be beneficial.